1. Field
Exemplary embodiments of the present invention relate to semiconductor design technology, and more particularly, to a semiconductor device with an edge-delayed signals generation circuit and a method of driving the same.
2. Description of the Related Art
In general, two or more delay circuits are used to generate edge-delayed signals by delaying an enable edge and a disable edge of one signal, respectively. For example, to obtain an enabling signal for a bit line sense amplifier and a driving signal for a word line, a first delay circuit for delaying the rising edge of an active signal and a second delay circuit for delaying the falling edge of the active signal may be used.
When the delay circuits are used as described above, the generation of accurate signals are limited because delay amounts set in respective delay circuits are not the same in view of design characteristics. That is, there is a problem in that the edge-delayed signals whose enable edge or disable edge have been delayed by a specific delay amount are not generated. Furthermore, if the delay circuits are formed of a D flip-flop chain or an inverter chain, it may not be possible to obtain a precise delay amount and to reduce a circuit area due to the delay circuits that are overlapped.